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SP5054 2.6ghz 3-wire bus controlled synthesiser ds3048 issue 3.4 may 1996 ordering information SP5054 kg dpas (18-lead plastic package) SP5054s kg mpas (16-lead miniature plastic package) the SP5054 is a single-chip frequency synthesiser designed for satellite tv tuning systems. it is a programming variant of the sp5055, allowing the design of one tuner with either i 2 c bus or 3-wire bus format, depending on which device is inserted. the SP5054, when used with a satellite varactor tuner, forms a complete phase locked loop tuning system. the circuit consists of a divide-by-16 prescaler with its own preamplifier and a 14/15-bit programmable divider controlled by a serially-loaded data register. four independently programmable open-collector outputs are included. the device has four modes of operation, selected by the mode select input; these modes are summarised in table1. the comparison frequencies are obtained by the division of the output of a 4mhz crystal controlled on-chip oscillator. the phase comparator has a charge pump output with an output amplifier stage around which feedback may be applied. only one external transistor is required for varactor line driving. features complete 2?ghz single chip system 62?khz, 100khz and 125khz step size low power consumption (325mw typ.) programming compatible with toshiba td6380, td6381 and td6382 * pin compatible with sp5055 * low radiation varactor drive amplifier disable charge pump disable single port 18/19 bit serial data entry four controllable outputs esd protection ? * see notes on pin compatibility ? normal esd handling precautions should be observed applications satellite tv high if cable tuning systems figure 1 - pin connections ?top view charge pump crystal mode select data clock port p4 port p3 port p2 port p1 drive output v ee rf input rf input v cc nc nc lock enable 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 SP5054 SP5054s 1 8 charge pump crystal mode select data clock port p4 port p3 port p2 mp16 16 9 drive output v ee rf input rf input v cc lock enable port p1 dp18
2 SP5054 electrical characteristics t amb = 220 c to 180 c, v cc = 14?v to 15?v. frequency standard = 4mhz. all pin connections refer to dp package. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. supply current prescaler input voltage prescaler input voltage prescaler input impedance input capacitance high level input voltage low level input voltage high level input current low level input current low level input current high level input current low level input current clock inout hysteresis clock rate data set up time, t 2 data hold time, t 3 enable set up time, t 1 enable hold time, t 5 clock-to-enable time, t 4 charge pump output current charge pump output leakage current drift due to leakage charge pump drive output current charge pump amplifier gain oscillator temperature stability oscillator stability with supply voltage recommended crystal series resistance crystal oscillator drive level crystal oscillator source impedance ports and lock output sink current port leakage current varactor drive amplifier disable charge pump disable typ. value conditions characteristic pin 14 15,16 15,16 4,5,10 4,5,10 4,5,10 5 4,10 3 3 5 5 4 4 10 10 10 1 1 18 2 2 6-9,11 6-9 10 4 50 100 3 0 300 600 300 600 300 1 10 10 2 350 2 350 65 50 2 04 6 150 6400 40 2 400 80 400 400 v cc 07 1 5 2 250 700 2 700 05 6 5 5 2 2 200 10 units min. max. ma mvrms mvrms ? pf v v a a a a a v mhz ns ns ns ns ns a na mv/s ma ppm/ c ppm/v ? mv p-p ? ma a a a v cc = 5v 500mhz to 26ghz sinewave 120mhz and 500mhz, see fig. 6 v in = 55v, v cc = 55v v in = 0v, v cc = 55v v in = 0v, v cc = 55v v in = 55v, v cc = 55v v in = 0v, v cc = 55v see fig. 4 see fig. 4 see fig. 4 see fig. 4 see fig. 4 v pin 1 = 20v v pin 1 = 20v at collector of external transistor v pin 18 = 07v i pin 18 = 100 a parallel resonant crystal (note 1) nominal spread = 6 15% v out = 07v v out = 132v v in < 0v v in < 0v note 1. the maximum resistance quoted refers to all conditions, including start-up.
3 SP5054 absolute maximum ratings all voltages are referred to v ee = 0v supply voltage rf input voltage port voltage prescaler dc offset loop amplifier dc offset crystal oscillator dc offset data bus inputs storage temperature junction temperature dp18 thermal resistance, chip-to-ambient dp18 thermal resistance, chip-to-case mp16 thermal resistance, chip-to-ambient mp16 thermal resistance, chip-to-case power consumption at 55v parameter conditions 12 13,14 6-9 6-9 13-14 1,16 2 4,5,10 max. min. units 7 25 14 6 v cc 1 03 v cc 1 03 v cc 1 03 v cc 1 03 1 150 1 150 78 24 111 41 484 value 2 03 2 03 2 03 2 03 2 03 2 03 2 03 2 55 v v p-p v v v v v v c c c/w c/w c/w c/w mw port in off state port in on state with v cc applied pin SP5054 SP5054s 14 15,16 6-9 6-9 15,16 1,18 2 4,5,10 figure 2 - typical input impedance j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 s 11 z o = 50 ? 2?ghz frequency marker step = 500mhz
4 SP5054 figure 3 - block diagram of SP5054 functional description the SP5054 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscilla- tor, so forming a pll frequency synthesised source. the system is controlled by a microprocessor via a stand- ard data, clock and enable three-wire data bus. the data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. the clock input is disabled during enable low periods. new data words are only accepted by the internal data buffers from the shift register on a negative transition of the enable, so giving improved fine tune facility for digital afc etc. the data sequence and timing follows the format shown in fig. 4. the frequency is set by loading the programmable divider with the required 14/15 bit divisor word. the output of this divider, f pd , is fed to the phase comparator where it is compared in phase and frequency domain to the internally generated comparison frequency, f comp . f comp is obtained by dividing the output of an on-chip crystal controlled oscillator. the crystal frequency used is generally 4mhz, which gives an f comp of 3?0625/6?5/ 7?125khz and, when multiplied back up to the synthesised lo, gives a minimum step size of 62?/100/125khz, respec- tively. the programmable divider is preceded by an input rf preamplifier and high speed, low radiation prescaler. the preamplifier is arranged to be self oscillating, so giving excel- lent input sensitivity. the SP5054 contains an improved lock detect circuit which generates a flag when the loop has attained lock. ?n lock?is indicated by high impedance state. the SP5054 contains 4 general purpose open collector outputs, ports p1-p4, which are capable of sinking at least 10ma. these outputs are set by the remaining four bits within the normal data word. notes on pin compatibility the SP5054 may be used in sp5055 applications which require 3-wire bus as opposed to i 2 c bus data format. in sp5055 applications where the reference crystal is grounded to pin 3, a small modification is required to ground the crystal as shown in fig. 5. appropriate connections must also be made to the mode select input (see table 1). in mode 3, the SP5054 is pro- gramming compatible with the toshiba td6380, in modes 0 and 2 with the td6381 and in mode 1 with the td6382. mode select input voltage 0925v cc to v cc 0675v cc to 0825v cc open circuit 0v to 0325 v cc programmable divider bit length 14 15 15 15 mode 3 2 1 0 reference divider ratio 512 512 1024 640 frequency step size (khz) * 125 125 625 100 maximum operating frequency (ghz) * 20479 25 20479 25 table 1 - SP5054 modes of operation. * frequencies stated apply when using a 4mhz crystal. 4 16 prescaler rf in rf in clock data enable mode select data input interface pre amp data clock 14 / 15 bit programmable divider 14 / 15 bit divider ratio latch control output buffer drive output p4 p3 p2 p1 ports phase comp f f pd charge pump lock detect f comp reference divider 4 512 / 640 / 1024 osc 4mhz mode select v cc crystal charge pump v ee cp dis va dis lock
5 SP5054 clock p1 p2 p3 p4 msb 2 17 2 16 2 15 2 14 2 13 2 12 2 0 2 1 2 2 lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? frequency data (lsb = 125khz) p1 p2 p3 p4 msb 2 18 2 17 2 16 2 15 2 14 2 13 2 0 2 1 2 2 lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? frequency data enable data (mode 3) data (modes 0, 1, 2) t 1 t 4 t 2 t 3 t 5 t 1 = enable set-up time t 2 = data set-up time t 3 = data hold time t 4 = clock-to enable time t 5 = enable hold time clock enable data lsb = 125khz (mode 2) 625khz (mode 1) 100khz (mode 0) figure 4 - data format and timing
6 SP5054 figure 5 - typical application (f step = 125khz) figure 6 - typical input sensitivity oscillator output 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 SP5054 1n 1n 2n3904 47n 22k 180n 18p 4mhz crystal 1 5v 10k 47k 10n satellite tuner varactor drive 1 12v 1 30v 22k control micro p4 p3 p2 p1 lock enable data clock mode v t 01 400 150 100 50 120 1000 2000 2600 3000 frequency (mhz) v in (mv rms into 50 ? ) operating window
7 SP5054 figure 7 - SP5054 input/output interface circuits v cc v ref rf inputs 550550 v cc 170 charge pump drive output input clock crystal port mode select rf input loop amplifier enable and data inputs clock input reference oscillator output ports p1-p4 mode select input
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